1. Field of the Invention
The present invention generally relates to a method and apparatus for manipulating a group of instances of a circuit design database, and more particularly relates to a method and apparatus for associating selected instances within the circuit design database, and for performing a group operation thereon.
2. Description of the Prior Art
The design process for all integrated circuits is composed of several discrete operations. Initially, the proposed functionality for a circuit is analyzed by one or more chip designers. These designers define the logical components of the circuit and their interactions by specifying the logic design using design capture tools. These design capture tools are commonly implemented in software executing on an engineering workstation, with well-known input devices being used to receive design information from the chip designer, and output devices, such as computer displays, being used to provide visual feedback of the design to the designer as it is being constructed. Such software is typically implemented as part of an electronic design automation (EDA) system. Specifically, the design entry operation involves generating a description of the logic design to be implemented on the circuit chip in an appropriate machine-readable form. Chip designers generally employ hierarchical design techniques to determine the appropriate selection and interconnection of logic and/or memory devices which will enable the chip to perform the desired function. These techniques involve describing the chip""s functionality at various levels of abstraction, ranging from the most general function performed by the chip to the precise functions performed by each logic and/or memory element on the chip.
A common method for specifying the integrated circuit design is the use of hardware description languages. This method allows a circuit designer to specify the circuit at the register transfer level (also known as a xe2x80x9cbehavior descriptionxe2x80x9d). Using this method, the circuit is defined in small building blocks. The names of the building blocks are specified by the circuit designer. Thus, they usually are logical names with specific functional meaning.
Encoding the design in a hardware description language (HDL) is a major design entry technique used to specify modern integrated circuits. Hardware description languages are specifically developed to aid a designer in describing a circuit. These languages often contain specific functions and syntax to allow complex hardware structures to be described in a compact and efficient way.
Another common method for specifying the integrated circuit design is the use a schematic capture tool. A schematic capture tool allows the circuit designer to directly enter the schematics for the circuit design. Unlike a hardware description language, the resulting schematics often completely specify the logical and functional relationships among the components of the design.
It is useful to distinguish between those components of an integrated circuit design called cells, provided by a silicon chip vendor as primitive cells (i.e., leaf candidates), and the user-defined hierarchy blocks built upon them. One way is to speak of a xe2x80x9ccell libraryxe2x80x9d vs. a xe2x80x9cdesign libraryxe2x80x9d as two separate libraries, both of which are available to subsequent designs. Alternatively, at least initially, a design library contains a cell library. A cell library is a database containing detailed specifications on the characteristics of each logical component available for use in a design. Initial cell library contents are usually provided by the chip vendor. The components in the cell library are identified by the generic description of the component type. For example, the term xe2x80x9cNANDxe2x80x9d for a NAND gate is its type description and distinguishes this component from others such as OR gates, flip-flops, multiplexors, and so on. A two-input NAND gate might be of type 2NAND. When a 2NAND component is specified as part of a given circuit design, it is given an instance name, to distinguish it from all other 2NAND gates used in the circuit. The instance name typically includes the instance names of all parent instances by concatenation when defining the instance in the context of the chip.
The user-defined blocks can then be used to design larger blocks of greater complexity. The user-defined blocks are added to the design library, which grows from the additions of new design modules as the design evolves. The top level of the design hierarchy may be a single block that defines the entire design, and the bottom layer of the hierarchy may consist of leaf cells, the cells (i.e., the logical components) that were originally provided in the cell library. Note that the hierarchy is typically structured as a special kind of a graph called a tree. This resulting data structure is called a detailed (or gate-level) description of the logic design.
The generation of the detailed description is often accomplished by logic design synthesis software for HDL entry. The logic design synthesis software generates a gate-level description of user-defined input and output logic, and also creates new gate-level logic to implement user-defined logical functions. Constituent parts of new gate-level logic created during each pass through the logic design synthesis software are given computer-generated component and net names. Each time the logic design synthesis software is executed for the integrated circuit design, the component and net names which are generated by the software, and not explicitly defined by the user, may change, depending on whether new logic has been added to or deleted from the integrated circuit design. Typically, the logic design synthesis software is executed many times during the integrated circuit design process, because errors may be detected during the simulation and testing phases of the design cycle and then fixed in the behavioral description.
The output of the design capture and synthesis tools is a logic design database which completely specifies the logical and functional relationships among the components of the design. Once the design has been converted into this form, it may be optimized by sending the logic design database to a logic optimizer tool implemented in software. The logic optimizer may remove logic from the design that is unnecessary, or otherwise improve the overall efficiency of the design. It is noted, however, that this action typically affects the component and net names generated by the logic synthesis tool.
It is also necessary to verify that the logic definition is correct and that the integrated circuit implements the function expected by the circuit designer. This verification is currently achieved by estimated timing and simulation software tools. The design undergoes design verification analysis in order to detect flaws in the design. The design is also analyzed by simulating the device resulting from the design to assess the functionality of the design. If errors are found or the resulting functionality is unacceptable, the designer modifies the behavior description as needed. These design iterations help to ensure that the design satisfies its requirements. As a result of each revision to the design, the logic design synthesis-generated instance and net names may completely change. Further, the changes made by the logic optimizer may not be precisely known. Thus, the EDA tools downstream in the design process from the logic design synthesis software must be re-executed on the entire design.
After timing verification and functional simulation has been completed on the design, placement and routing of the design""s components is performed. These steps involve assigning components of the design to locations on the integrated circuit chip and interconnecting the components to form nets. This may be accomplished using automated place and route tools.
Because automatic placement tools may not yield an optimal design solution, particularly for high performance designs that have strict timing and physical requirements, circuit designers often manually place critical circuit objects (e.g. cells or regions) within the boundary of the integrated circuit. This may be accomplished by using a commercially available placement directive tool (also known as a floorplanning tool), typically implemented in software. The placement tool may include a graphics terminal that provides the circuit designer with visual information pertaining to the circuit design. This information is typically contained in several different windows.
A floorplanning window may display a graphical representation of, for example, the die area of an integrated circuit, the placed objects and connectivity information. Similarly, a placed physical window may display the alphanumeric names of all placed cells and hierarchical regions. An un-placed physical window may display the alphanumeric names of all un-placed cells and hierarchical regions. A logic window may display a hierarchical tree graph of the circuit design.
During the placement process, the circuit designer may select the name of a desired object from the un-placed physical window displaying the un-placed objects. After this selection, the placement tool may retrieve the physical representation of the selected object, and the circuit designer may use the cursor to position the physical representation of the selected object within the floorplanning window. The placement tool may then move the alphanumeric instance name of the selected object from the un-placed physical window to the placed physical window to indicate the placement thereof.
To edit the placement of desired objects, the circuit designer may select the desired physical representation of the object from the floorplanning window using a pointing device. The circuit designer may, for example, draw a rectangle around the desired objects to affect the selection. After selection, the circuit designer may instruct the placement tool to perform a desired editing function on the selected objects.
Some placement tools may allow the circuit designer to select a desired level of hierarchy or region as the current working environment, or xe2x80x9ccontextxe2x80x9d. When the context is set, all of the objects existing at the next lower level in the circuit design hierarchy are displayed in one of the physical windows, thus making them available for placement or editing. These objects are called children objects of the selected context, and may include other hierarchical objects, including regions and/or cells. Thus, a context may include a mixture of regions and cells.
In this environment, circuit designers may perform preliminary placement by first placing selected regions. In some placement tools, the outer boundary of the regions is appropriately sized to accommodate all underlying objects, even though all of the objects may not yet be placed. The circuit designer may then rely on an automated placement tool to subsequently place the underlying objects within the boundary of the region. If more detailed placement is required because of timing, physical or other constraints, selected lower level regions or cells may be manually placed by the circuit designer.
A goal of manual placement may be to minimize the net length between objects, and in particular, to minimize the net lengths of those nets that are critical to the performance of the overall circuit design. A shorter net length may produce a reduced capacitance, and may thus directly increase the performance of the design. Further, because of the shorter net lengths, there may be less net cross over and routing congestion, and the resulting design may be smaller in overall size.
Vectored nets are often given special consideration by circuit designers, particularly since vectored nets may correspond to the critical data and/or address paths within a circuit design. For this reason, a large percentage of the manual placement performed by a circuit designer may involve the placement of objects that drive or receive vectored nets.
After selected objects have been manually placed by a circuit designer, it may be desirable to analyze the resulting net connectivity to determine the desirability of the placement. Prior art placement tools typically only allow the circuit designer to view all placed cells, and all net connectivity associated therewith. The net connectivity is typically displayed using fly wires or the like. In complex designs, however, there may be many overlapping fly-wires that appear as a xe2x80x9crats netsxe2x80x9d, and thus it may be difficult to identify those flywires that are associated with a particular data path. In addition, the circuit designer typically may not be able to view those nets that are associated with yet un-placed objects, and thus may not be able to identify potential regions of high routing congestion. All of these limitations may reduce the overall effectiveness of a placement tool.
The present invention overcomes many of the disadvantages of the prior art by providing a method and apparatus for selectively viewing nets within a database editor tool. The present invention provides four primary features for selectively viewing nets. First, the present invention contemplates selecting a number of objects, and viewing only those nets that are either driven from or received by the selected objects. In a preferred embodiment, the number of objects are placed objects within a placement tool. Second, for those nets that are selected, and that are also coupled to un-placed cells, the present invention contemplated providing fly-wires from the corresponding selected objects to a predetermined location representative of an approximate expected placement location for the un-placed cells. Third, the present invention contemplated providing a vector filter which may permit only vectored nets with a selected bus width range to be viewed. Finally, the fourth feature of the present invention contemplates providing a means for selectively viewing only those nets that cross a predetermined hierarchical boundary within the circuit design database.
It is recognized that any database editor tool may be used or adapted to be used in accordance with the present invention. Some examples of database editor tools that may be used include schematic entry tools, place and route tools, simulation tools, floorplanning tools, or any other tool that allows the circuit designer to view and/or edit a representation of a circuit design. As indicated above, and in a preferred embodiment, the database editor tool is a placement tool (e.g. floorplanning) tool.
The first feature, as described above, allows a circuit designer to select a number of objects, and view only those nets that are either driven from or received by the selected objects. This feature may be particularly useful when a circuit designer desires to view a vectored net. The circuit designer may select the objects that either drive or receive the bits of a vectored net, and the present invention may then display only those nets on the display device. By examining only the nets associated with the vectored net, the circuit designer may more readily evaluate the placement of the objects that drive or receive the nets.
In a preferred embodiment, the circuit designer may select all objects that are associated with a vectored net by using a stack mode feature. A stack mode feature may allow the circuit designer to select all of the objects associated with a vectored net by simply selecting one of the associated objects. A further discussion of the stack feature can be found in U.S. patent application Ser. No. 08/789,028, filed Jan. 27, 1997, entitled xe2x80x9cMethod and Apparatus for Associating Selected Circuit Instances and for Performing a Group Operation Thereonxe2x80x9d.
Finally, it is contemplated that the first feature may be used in conjunction with any database editor tool, as described above. However, in a preferred embodiment the database editor tool is a placement tool, and the selected objects are placed objects within a placement database.
The second feature, allows the circuit designer to display not only the portion of the nets that extend between selected objects, but estimates the position of the portion of the nets that extend to yet un-placed objects. For example, if a first placed object drives a net, and a second placed object receive the net, the present invention may display a flywire between the first object and the second object. However, if a third un-placed object also receive the net, the present invention contemplates displaying a flywire to an estimated placement location for the third un-placed object. This may help identify potential regions of high routing congestion and/or suggest to a circuit designer a desirable placement location for the third un-placed object.
The third feature of the present invention, as described above, contemplated providing a vector filter which may permit only vectored nets with a selected bus width range to be viewed. That is, the circuit designer may specify a bus width range, and a vector filter may then filter those nets that fall within the specified bus width. The resulting nets may then be displayed on a display device. This feature may allow a circuit designer to, for example, display only those nets within a circuit design that are directly associated with a selected data or address path. This may allow the circuit designer to more readily analyze the placement of the objects that are associated with the selected data or address path.
Finally, the fourth feature of the of the present invention contemplates providing a means for selectively viewing only those nets that cross a predefined hierarchical boundary within the circuit design database. This feature may allow a circuit designer to more readily identify those nets that enter or exit a particular region. Further, this feature may enable a circuit designer to more readily trace a net through the circuit design hierarchy.